发明名称 Testing memory cells with hysteresis curve e.g. for FRAM
摘要 The method involves applying test voltages to the memory cells (Cfe, T) during a test procedure. The test voltages are varied in steps to detect memory cells with deformed hysteresis curves. The memory cells are ferroelectric. The plate voltage applied to a ferroelectric storage capacitor is varied, or a reference voltage that is compared with the read voltage read from a memory cell is varied. Alternatively, the voltage applied to a word line, or the write voltage applied to the memory cell is varied.
申请公布号 DE19957124(A1) 申请公布日期 2001.05.31
申请号 DE19991057124 申请日期 1999.11.26
申请人 INFINEON TECHNOLOGIES AG 发明人 POECHMUELLER, PETER
分类号 G11C11/22;G11C29/50;(IPC1-7):G11C29/00 主分类号 G11C11/22
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