| 摘要 |
The active areas and the body regions for the LV MOS transistors, for the HV MOS transistors and for the EPROM cells are formed on a silicon substrate, a layer of thermal oxide is formed, and a layer of polycrystalline silicon is formed on it, the last-mentioned layer is removed selectively to form the floating gate electrodes (13a) of the cells, the source and drain regions of the cells are formed, the silicon of the areas of the HV MOS transistors is exposed, a layer of HTO oxide is formed and nitrided, the silicon of the areas of the LV MOS transistors is exposed, a layer of thermal oxide (16) is formed on the exposed areas, a second layer of polycrystalline silicon is deposited and is then removed selectively to form the gate electrodes of the LV and HV MOS transistors (17c, 17b) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV and HV MOS transistors are formed. Owing to the simultaneous formation of the gate dielectric of the HV MOS transistors and the intermediate dielectric of the cells, and the use of a material (nitrided HTO oxide) which is impermeable to the oxygen atoms of the subsequent thermal oxidation, the number of the operations in the process is smaller than in the prior art process. <IMAGE> |
