| 摘要 |
PROBLEM TO BE SOLVED: To remove noises of a timing controller and to simplify a logic formation, by using high-frequency clock signals only at the data entry and by using low-frequency clock signals in performing other actions. SOLUTION: One vertical period is divided into eight sub-field driving period, and each sub-field driving period is divided into three steps, namely, (a) an entering or erasing step of all pixels, (b) a data entry step, and (c) a discharge- sustaining step. The steps (a) and (b) are formed with the same time per each sub-field, but the step (c) is formed with a different time decided by a weighted value given to each sub-field. Low-frequency (2 MHz) clock signals generated from secondary clock generator 34 are used in the steps (a) and (c), in which a low-speed clock is required to decrease glitch noises, and high-frequency (50 MHz) clock signals generate from primary clock generator 32 are used in the step (b), in which a high-speed clock is required. |
