| 摘要 |
In a nonvolatile semiconductor memory device using a stacked gate structure type transistor as a memory cell, an N-type well is formed on the surface of a P-type silicon substrate, and a plurality of P-type wells are formed on the surface of the N-type well. The P-type wells are electrically isolated by trenches. A plurality of memory cells are formed on each of the P-type wells, and a P-type contact layer, which is connected to a bias circuit, is formed thereon. When information is read, a reverse bias voltage is selectively applied by the bias circuit between the P-type silicon substrate and the P-type well not including an N-type source diffusion layer of a selected memory cell. If, therefore, the threshold voltages of non-selected memory cells are heightened, the leak current flowing through the non-selected memory cells connected to the same wiring as that connected to the selected memory cell, can be reduced in the read mode even though the threshold voltages of the memory cells are set to a low value in the erase mode.
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