发明名称 TIMING IMPROVING METHOD
摘要 PROBLEM TO BE SOLVED: To improve the timing of a timing violating path while suppressing the degradation of the timing of a timing restriction keeping path to be small. SOLUTION: After cells are arranged in a step ST2, a path violating a timing restriction is extracted in a step ST3. Then, the timing of the timing violating path is improved in a step ST4. The timing is improved by calculating a wiring length for which weight inversely proportional to the driving ability of an element for driving the wiring is multiplied with the length of the wiring as the evaluation of the wiring length on the timing violating path and minimizing the total sum value of the weighted wiring length. Thus, since a net is selected in the descending order of a timing improving effect from the nets on the timing violating path and the net length is shortened, the timing of the timing violating path is effectively improved while lowering the possibility of changing the arranging position of the driving element positioned on the restriction keeping path as well.
申请公布号 JP2001148425(A) 申请公布日期 2001.05.29
申请号 JP19990329064 申请日期 1999.11.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIBASHI NORIKO;KUROKAWA KEIICHI;TOYONAGA MASAHIKO
分类号 H01L21/82;G06F17/50;(IPC1-7):H01L21/82 主分类号 H01L21/82
代理机构 代理人
主权项
地址