| 摘要 |
A microprocessor configured to predecode instructions with variable address and operand lengths into a uniform format with constant address and operand lengths is disclosed. The microprocessor may comprise a predecode unit configured to receive instruction bytes from a main memory subsystem. The predecode unit is configured to detect instructions having prefix bytes that override default operand and address field lengths. This information, combined with the instruction's default operand and address length, allows the predecode unit to expand addresses and operands that are shorter than the predetermined uniform length. The operands and addresses are expanded by padding them with constants. Once the instructions are padded to a uniform format, they are stored in an instruction cache. An address translation table may be used to translate fetch addresses, thereby compensating for the offset created by the padding constants. The microprocessor may also be configured to detect the execution of instructions that modify segment default address and operand lengths. Upon detecting the execution of this type of instruction, the microprocessor may be configured to flush the contents of the instruction cache and address translation table. An optional secondary cache may store unpadded versions of the instructions to speed rebuilding of the instruction cache and address translation table after a flush. A computer system and method for predecoding instructions are also disclosed.
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