发明名称 Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
摘要 Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.
申请公布号 US6239499(B1) 申请公布日期 2001.05.29
申请号 US19980198208 申请日期 1998.11.23
申请人 LSI LOGIC CORPORATION 发明人 ZHAO JOE W.;DOU SHUMAY X.;CATABAY WILBUR
分类号 H01L23/544;(IPC1-7):H01L23/544 主分类号 H01L23/544
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