发明名称 |
Fail-safe timing circuit and on-delay circuit using the same |
摘要 |
The present invention relates to a fail-safe timing circuit and on-delay circuit which does not produce an erroneous output where the delay time is shortened, due to a fault. The timing circuit comprises: an oscillation circuit (11) which produces a timing output from a cathode terminal of a PUT after a predetermined time lapse from input of an input signal (VIN); and a monitoring circuit (12) for monitoring for the normalcy of the oscillation circuit (11). Moreover the on-delay circuit comprises a self hold circuit (13) with an output signal (Vo) generated from the monitoring circuit (12) only when the normalcy of the oscillation circuit (11) is verified by generation of a falling signal of a cathode terminal voltage of the oscillation circuit (11), input to a second terminal (b), and the input signal (VIN) input to a first terminal (a), which produces an output signal only when the two input signals are both at a higher level than a power source potential.
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申请公布号 |
US6239956(B1) |
申请公布日期 |
2001.05.29 |
申请号 |
US19970913143 |
申请日期 |
1997.08.13 |
申请人 |
THE NIPPON SIGNAL CO., LTD. |
发明人 |
SHIRAI TOSHIHITO;FUTSUHARA KOICHI |
分类号 |
H03K19/007;H03K3/3525;H03K17/292;H03K17/78;H03K19/0175;(IPC1-7):H02H7/00 |
主分类号 |
H03K19/007 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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