| 摘要 |
A PCI bus controller which operates according to the PCI clock run protocol, without the complexity of a typical PCI bridge. This provides the power savings of Mobile PCI Clock run without the overhead, cost and complexity of a PCI to PCI bridge. This is accomplished by supplying a clock run controller, which sits on between the upstream PCI bus and a downstream PCI device, monitors traffic on the bus to determine if the PCI device is being actively accessed. If not, the clock to the PCI device is controlled according to the clock run protocol.
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