发明名称 |
System for memory based interrupt queue in a memory of a multiprocessor system |
摘要 |
An interrupt mechanism which reduces or eliminates the need for an interrupt status register while at the same time provides suitable information to a host or other processor with respect to the cause and parameters surrounding an interrupt signal. An interrupt queue is maintained in shared memory accessible by both a host and an interrupting agent. The interrupt queue has a capacity or two or more separate interrupt requests, either from a same interrupting agent or from two different interrupting agents. As interrupting agents write to the interrupt queue, an agent current interrupt pointer (ACIP) is incremented to a next position in the interrupt queue. As the host services interrupts, the current host pointer is incremented to clear the serviced interrupt request entry. |
申请公布号 |
US6240483(B1) |
申请公布日期 |
2001.05.29 |
申请号 |
US19980140673 |
申请日期 |
1998.08.26 |
申请人 |
AGERE SYSTEMS GUARDIAN CORP. |
发明人 |
GUTTA SRINIVASA;SOTO WALTER G.;PARTHASARATHY RAMAN |
分类号 |
G06F11/34;G06F12/06;H04L7/00;H04L7/02;(IPC1-7):G06F13/24 |
主分类号 |
G06F11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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