发明名称 Low-voltage content addressable memory cell with a fast tag-compare capability using partially-depleted SOI CMOS dynamic-threshold techniques
摘要 This invention discloses a content addressable memory (CAM) cell having a SRAM portion and a tag-compare portion. The tag-compare portion includes six NMOS transistors, designated as M7 to M12, wherein a source of M7 is connected to a drain of M8, a drain of M7 is connected to a match line ML, a source of M8 is grounded; a body of M7 and a body of M8 are tied together at a source of M11, a gate of M7 and a gate of M11 are tied together to a first node n1, a gate of M8 and a drain of M11 are connected to a first digit line DLB; and a source of M9 is connected to a drain of M10, a drain of M9 is connected to said match line ML, a source of M10 is grounded; a body of M9 and a body of M10 are tied together at a source of M12, a gate of M9 and a gate of M12 are tied together to a second node n2, a gate of M10 and a drain of M12 are connected to a second digit line DL. The first and second nodes n1 and n2 are internal storage nodes of the SRAM portion.
申请公布号 US6240004(B1) 申请公布日期 2001.05.29
申请号 US20000597275 申请日期 2000.06.19
申请人 KUO JAMES B.;LIU SHENG-CHE 发明人 KUO JAMES B.;LIU SHENG-CHE
分类号 G11C15/04;(IPC1-7):G11C15/00 主分类号 G11C15/04
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