| 摘要 |
In a synchronous semiconductor storage device, upon latching potentials of a bit line by a sense amplifier in a read operation, a bit line disconnecting circuit disconnects the bit line and an associated reference line from the sense amplifier until a next read operation. At the same time, a virtual GND line disconnecting circuit disconnects a corresponding virtual GND line from the ground potential until the next read operation. After the disconnection of the bit line, the reference line, and the virtual line, the precharge operation of the bit line and virtual line by the VREF level supply circuits is performed in parallel with the amplifying operation by the sense amplifier. This allows an access with a CAS latency of 3.
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