发明名称 |
VIDEO IMAGE SYNTHESIS ARITHMETIC PROCESSING UNIT, ITS METHOD AND SYSTEM |
摘要 |
PROBLEM TO BE SOLVED: To provide a video image synthesis arithmetic processing unit that can asynchronously extract a synthesis image from a plurality of video signals which arrive asynchronously with a small time delay independently of input signals. SOLUTION: Each of frame memories writes line data of a plurality of video signals via line buffers 2A-2C, and the line data in each frame memory are read through each of read buffers 4A-4C at a point of a read time. An arithmetic section 5 applies an arithmetic operation of image synthesis for each pixel of image data of a plurality of the video image line data according to synthesis control instruction data corresponding to pixels read from a control memory 8. A receiver side receiving a plurality of source video images and control data can generate a synthesized video image or generate a synthesized video image in response to a request of a user by replacing part of the source video image with a video image of the user. By applying increase/decrease processing to address parts of a plurality of video signals, a synthesis image and a stereoscopic image that meet needs of a viewer can be generated in real time.
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申请公布号 |
JP2001148806(A) |
申请公布日期 |
2001.05.29 |
申请号 |
JP19990331191 |
申请日期 |
1999.11.22 |
申请人 |
NATL INST OF ADVANCED INDUSTRIAL SCIENCE & TECHNOLOGY METI |
发明人 |
MORIKAWA OSAMU |
分类号 |
H04N5/265;G09G5/00;G09G5/377;H04N1/387;H04N5/272;(IPC1-7):H04N5/265 |
主分类号 |
H04N5/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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