| 摘要 |
The number (Nc) of conductor regions and the number (Ncell(i)) of cells constituting each conductor region (ci) are calculated from the result of a configuration simulation. Each conductor region (ci) is judged whether or not the number (Ncell(i)) of cells thereof is less than a minimum cell count (Ncellmin) for recognition as an electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is not less than the minimum cell count (Ncellmin) is regarded as the electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on a previously set one of the top, bottom, left-hand, right-hand, front and rear sides of the conductor region (ci). For example, it is assumed that Nc=4, Ncell(1)=16, Ncell(2)=8, Ncell(3)=1, Ncell(4)=1, Ncellmin=5 and a conductor region having the number of cells less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on the top side of the conductor region, conductor regions (c1 and c2) are regarded as electrodes or interconnect lines and conductor regions (c3 and c4) are replaced with a dielectric (epsi3). After the processing of all conductor regions are complete, a capacitance simulation, for example, is performed precisely. The influences of errors caused by the configuration simulation using the cells are reduced for execution of another simulation.
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