发明名称 |
Multiple bank simultaneous operation for a flash memory |
摘要 |
An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit. |
申请公布号 |
US6240040(B1) |
申请公布日期 |
2001.05.29 |
申请号 |
US20000526239 |
申请日期 |
2000.03.15 |
申请人 |
ADVANCED MICRO DEVICES, INC.;FUJITSU LIMITED |
发明人 |
AKAOGI TAKAO;CLEVELAND LEE EDWARD;NGUYEN KENDRA |
分类号 |
G11C16/02;G06F12/00;G06F12/06;G11C16/06;G11C16/08;G11C16/10;G11C16/26;(IPC1-7):G11C8/00 |
主分类号 |
G11C16/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|