| 摘要 |
PROBLEM TO BE SOLVED: To prepare an efficient and highly accurate floor plan, with which it is not necessary to execute floor planning again because of trouble in detailed location of circuit blocks and detailed wiring between circuit blocks in a post- process, by preparing the floor plan of an entire chip by successively preparing partial floor plans with the area of one part on the chip as an object. SOLUTION: On the basis of circuit connection information 10 and layout information 11, an initial floor plan to become the starting point is prepared in a step S11. An internal chip area is divided into plural partial floor plan areas composed of circuit blocks in a step S17, it is decided whether a soft macro block exists in each of these partial floor plan areas or not and when the soft macro block exists, the partial floor plan is prepared for locating the circuit blocks by optimizing the terminal position of the soft macro block.
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