| 摘要 |
A self-timed domino control circuit for control of a data path is described which provides zero overhead latency and improved cycle time, while maintaining the delay insensitive characteristics of self-timed domino circuits. The data path includes sequential stages i-1, i and i+1, each of which performs a logic function on input signals supplied to it. Each stage requires a first time period for precharging and a second time period for evaluating. The logic function of stage i is evaluated when stage i+1 is precharging, and stage i is precharged when stage i+1 has completed evaluating, but before stage i+1 begins precharging, and when stage i-1 has completed precharging.
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