发明名称 Host adapter having a plurality of register sets and corresponding operating nodes
摘要 A memory architecture for a circuit such as a host adapter provides sections of memory used for different types of information and programmable sizes for the sections. Thus, the circuit can adapt memory configurations for different applications. Each section is divided into pages, and for each section, the circuit has a range of internal addresses that map to a current page in the section. Additionally, the circuit has several operating modes and several register sets. Each mode has a set of functions that the circuit performs and a register set that the circuit can access while operating in the mode. Currently accessible pages in the memory are selected according to the operating mode. In particular, the register sets include registers for pointers that identify pages currently accessible. When the circuit switches modes, the accessible register set changes, and changing the register set changes the pointers and which pages are accessible. Generally, the accessible register set and memory pages are selected according to the function of the mode. Accordingly, the internal address space for accessing registers and memory can be minimized, since only the registers and pages needed for the functions of a mode are accessible while the circuit operates in the mode.
申请公布号 US6240482(B1) 申请公布日期 2001.05.29
申请号 US19980089044 申请日期 1998.06.02
申请人 ADAPTEC, INC. 发明人 GATES STILLMAN F.;DEVANAGUNDY UDAY N.
分类号 H04Q11/04;(IPC1-7):G06F13/38 主分类号 H04Q11/04
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