发明名称 High speed address sequencer
摘要 A high speed address sequencer allows for a generation of address signals using a clock with higher frequency. The high speed address sequencer can be used in many semiconductor devices, especially in flash memory devices. By reducing a number of gate delays, the high speed address sequencer can generate all address signals in a reduced time period. By using an address signal as a clock for generation of some of the other address signals, the high speed address sequencer is allowed more time to generate all address signals with a given clock frequency. The reduction in the number of gate delays can be combined with the use of the address signal as a clock.
申请公布号 US6240044(B1) 申请公布日期 2001.05.29
申请号 US19990467649 申请日期 1999.12.20
申请人 FUJITSU LIMITED 发明人 AKAOGI TAKAO
分类号 G11C16/06;G11C8/04;G11C16/08;G11C16/30;G11C16/32;(IPC1-7):G11C8/00 主分类号 G11C16/06
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