| 摘要 |
<p>The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value. In the present invention, a voltage control type oscillator is not used, and since delay amounts of the first to nth delay circuits are controlled by the delay control value generated based on the phase comparison result, the delay clock generator can be constituted wholly by digital circuits and moreover can generate stable delay clocks.</p> |
