| 摘要 |
PROBLEM TO BE SOLVED: To improve the reliability of a device by preventing system down. SOLUTION: This cache memory device is provided with a primary cache memory 102 and a secondary cache memory 110 in a 4 way set associative system. When a parity error is generated in a certain entry in the primary cache memory 102, the replace of the pertinent way is inhibited, and data related with the entry are written back from the primary cache memory 102 to the secondary cache memory 110, and the entry in the primary cache memory 102 is invalidated, and the inhibition of the replace of the pertinent way is released. When access to the secondary cache memory 110 is performed, the data written back from the secondary cache memory 110 to the primary cache memory 102 are moved in so that the state before the generation of the parity error can be obtained. |
