发明名称
摘要 PURPOSE:To reduce the required amount of transmission data of quantization bits generated at every block. CONSTITUTION:The dynamic range DR of the block that is the difference of the maximum value MAX and the minimum value MIN is found at a subtraction circuit 7. A quantization step width generation circuit 9 generates quantization step width suitable for the dynamic range. Each image data from which the minimum value MIN is eliminated is quantized at a quantization circuit 11 with the quantization step width DELTA, and for example, a code signal DT of constant four bits is generated. Four sub blocks are formed by dividing one block. A comparator 13 compares the dynamic range DR' of the sub block with a threshold value TH-P, and generates an ID flag. The ID flag is supplied to a data conversion circuit 12, and in the sub block whose DR' is smaller than the threshold value TH-P, one representative code is generated from the data conversion circuit 12.
申请公布号 JP3170929(B2) 申请公布日期 2001.05.28
申请号 JP19930021981 申请日期 1993.01.14
申请人 发明人
分类号 H03M7/50;G06T9/00;H04N1/41;H04N1/415;H04N7/24;H04N19/00;H04N19/115;H04N19/126;H04N19/13;H04N19/136;H04N19/14;H04N19/176;H04N19/196;H04N19/423;H04N19/46;H04N19/65;H04N19/70;H04N19/85;H04N19/91;H04N19/98 主分类号 H03M7/50
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