发明名称 |
FAULT TOLERANT VIRTUAL VMEbus BACKPLANE DESIGN |
摘要 |
This invention provides fault tolerant capability for a Versa Module Eurocards backplane system design for high reliability applications. An approach of connecting two independent backplanes (10, 14) together electrically, but providing isolation capabilities in the event a failure was developed. The electrical connection or integrated bridge design provides a virtual connection between the two VME backplanes (10, 14) that is transparent to the end user. The integrated virtual VMEbus design provides a low latency, high bandwidth interconnect between modules (12, 16) whether located on the same local bus (10, 14) or the electrically isolatable bus (18). This dual-VME fault tolerant backplane design eliminates complete system failures due to single event failures.
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申请公布号 |
WO0137102(A2) |
申请公布日期 |
2001.05.25 |
申请号 |
WO2000US31405 |
申请日期 |
2000.11.15 |
申请人 |
HONEYWELL INC. |
发明人 |
ODEGARD, THOMAS, A.;LEVINE, AARON;HANSEN, BRYAN, P.;THOMAS, LARRY, J. |
分类号 |
G06F13/36;G06F13/00;G06F13/40;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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