发明名称 SEMICONDUCTOR MEMORY AND ITS CONTROL METHOD
摘要 <p>PROBLEM TO BE SOLVED: To keep a bias potential supplied to a bias circuit which is provided in a read-out circuit section always constant. SOLUTION: This device is provided with a separation circuit 41 potentially separating a bit line BLL and a sense bit line BLS, a bias circuit 42 receiving constant bias potential VBIAS and setting a potential of a sense bit line LBS, without depending on a potential of a sense line SA, a load circuit 43 connected to a sense line SA, an amplifier circuit 44 enlarging potential amplitude in a bit line BLL, sensing data of a selected memory cell, and outputting it, a bit line initializing circuit 46 performing initial setting of a bit line BLL with a prescribed timing, a sense line initializing circuit 47 performing initial setting of a sense line SA with a prescribed timing, and a bias potential generating circuit 48 generating a bias potential VBIAS.</p>
申请公布号 JP2001143485(A) 申请公布日期 2001.05.25
申请号 JP19990322548 申请日期 1999.11.12
申请人 TOSHIBA CORP 发明人 TAKANO YOSHINORI;TANZAWA TORU;TAURA TADAYUKI
分类号 G11C16/06;G11C7/12;G11C7/20;G11C16/24;G11C16/26;(IPC1-7):G11C16/06 主分类号 G11C16/06
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