发明名称 TEST DEVICE FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the labor and time at the time of calibrating reference devices in respective sites without reducing precision in an IC test device capable of testing plural IC chips in parallel having the plural sites each including measurement units and measurement unit diagnostic reference devices. SOLUTION: In this test device, the reference devices 34x-36x in the reference site 3x are measured by the measurement units 31x-33x and standard devices 7, 9. The measurement units 31x-33x are sequentially connected to the reference devices 34-36 of each the site 3 through a signal line 21 and a shut-off part 22 provided in each the site 3 to measure the reference devices 34-36. A host computer 5 compares both the measured values of the reference devices 34x-36x to calculate measurement errors in the measurement units 31x-33x, and correct the measured values of the reference devices 34-36 in each the site 3 with the measurement errors. Thereby, the reference devices 34-36 in each the site 3 are calibrated.
申请公布号 JP2001141777(A) 申请公布日期 2001.05.25
申请号 JP19990325725 申请日期 1999.11.16
申请人 SHARP CORP 发明人 MATSUMOTO TAKAZO
分类号 G01R31/28;G01R31/26;G01R35/00;(IPC1-7):G01R31/26 主分类号 G01R31/28
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