| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a flip flop control circuit reducing low frequency power noise, a processor and an operation method for the processor. SOLUTION: An FF control circuit 10 is provided with a clock generation circuit 11 which is connected to a digital circuit 1 having plural FFs and generates a first clock pulse where the frequency of an oscillator such as a crystal oscillator is set to be a basic frequency, a clock selection circuit 12 generating a second clock pulse for high speed processing of a frequency higher than the basic frequency, from the first clock pulse and outputting the first or second clock pulse in accordance with a control signal, a counter circuit 13 starting measuring the first or second clock pulse after a start signal is received when the states of plural flip flops are decided, setting the control signal and releasing the setting of the control signal after prescribed time passes and a clock distribution circuit 14 outputting the first or second clock pulse to the plural flip flops.</p> |
