发明名称 PACKET EXCHANGING DEVICE, CLOCK SIGNAL CONTROLLER FOR PACKET EXCHANGING DEVICE AND METHOD FOR CONTROLLING CLOCK SIGNAL
摘要 <p>PROBLEM TO BE SOLVED: To provide a packet exchanging device capable of suppressing power consumption by controlling an operation speed so as to be able to realize processing performance corresponding to the traffic volume of a packet. SOLUTION: In this packet exchanging device 100 provided with a packet processing part 110 processing packet exchange, a transmission line interface 120 that is for connecting the part 110 to a transmission line and allowing the part 110 to transmit and receive a packet and a system clock control part 130 controlling the operation clock of the part 110 and the interface 120, the part 110 is provided with a packet counter 114 counting the number of packets per preliminarily set unit time, and the part 130 is provided with a frequency dividing circuit 132 which performs frequency division of an output signal of an oscillator 131 and outputs an operation clock and a frequency division control part 133 setting the frequency division ratio of the circuit 132 on the basis of the counting results of the counter 114.</p>
申请公布号 JP2001144753(A) 申请公布日期 2001.05.25
申请号 JP19990326074 申请日期 1999.11.16
申请人 NEC CORP 发明人 HORIKAWA SOJI
分类号 H04L7/00;H04L12/02;H04L12/28;(IPC1-7):H04L12/02 主分类号 H04L7/00
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