| 摘要 |
PROBLEM TO BE SOLVED: To shorten and/or remove access latency, to shorten a code size, and to increase an execution speed by providing an improved branch operation instruction format which is realized by a pipeline-constituted processor, and powerful and elastic. SOLUTION: A processor using an exception dealing circuit regarding program branching operation composed of individual branch control and a branch instruction is disclosed. Before a branch address calculated according to a branch control instruction is stored and used by the branch instruction, it is checked whether or not there is an exception. Consequently, the need to certify high-order logic regarding a normal branch instruction address check is reduced, so the use of only effective addresses for following pipeline operation is guaranteed.
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