| 摘要 |
PROBLEM TO BE SOLVED: To readily form a high precision NPN transistor and capacity, without impairing reliability of a MISFET gate insulating film. SOLUTION: A gate electrode and the lower electrode of capacity are formed on a substrate, an insulating film 116 is deposited, the active region of an NPN and a capacity region are opened for depositing an insulating film 117, and a base is formed. The insulating film 117 is etched, and a sidewall is formed on the sidewall of the active region opening part of the NPN by the insulating film 117. Polycrystalline silicon 119 is deposited for etching the polycrystalline silicon 119 and the insulating film 116, the sidewall of a PMOS is formed, and the external base region of the NPN and the source/drain region of the PMOS are a formed. Then, the polycrystalline silicon 119 and the insulating film 116 are etched, the sidewall of an NMOS is formed, and the collector take-out region of the NPN and the source/drain region of the NMOS are formed.
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