| 摘要 |
<p>An interface card (10) for a network or other communication channel, with limited intelligence, is implemented using a relatively slower, and lower cost embedded processor (14), supported by dedicated hardware logic for the purpose of intercepting certain packets being received via the network or communication channel (16). The interface comprises the first port (16) on which incoming data is received at the data transfer rate of the network, a buffer (13) coupled to the port that stores received packets, and a second port (17) coupled with the buffer through which transfer of packets to the host (12) is executed. Packet filters (15) are coupled to the first port which identifies packets being stored in the buffer that have one of the plurality of variant formats. A processor is coupled with the buffer as well, and is responsive to the packet filter to process identified packets in the buffer. The pattern match logic includes mask logic circuits, circuits to generate a hash in response to bytes selected by the mask, and a comparator which compares the output of the hash logic with an expected hash.</p> |
