发明名称 |
EFFICIENT POWER PROCESSING MECHANISM IN PIPELINE PROCESSOR |
摘要 |
PROBLEM TO BE SOLVED: To provide a mechanism to enable an efficient processing of power in a pipeline processor. SOLUTION: This processor is provided with plural execution pipeline stages, the respective stages receive plural operand inputs and generate the results. A pipe file 409 at least with the same number of entries as the number of the execution pipeline stages is included in the processor. A pointer register is related to the respective execution pipeline stages. One value is stored in at least one of the pointer registers and one specified entry of the entries in the pipe file is displayed by its value. |
申请公布号 |
JP2001142700(A) |
申请公布日期 |
2001.05.25 |
申请号 |
JP20000286978 |
申请日期 |
2000.09.21 |
申请人 |
HITACHI LTD |
发明人 |
CHIIJUI PEN;RYUU CHUAEOAN |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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