| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay optimizing system for hierarchical LSI design, with which repeat processing from the layout of a post-process can be reduced without manually applying all the areas of sub-blocks of respective hierarchies. SOLUTION: An area calculating processing part 21 calculates the required area for the unit of sub-block from information on the number of cells in a circuit block inside a technology library 4 and an LSI chip area in an LSI chip area holding part 7 and stores this calculating processing result in an area value information storage part 3. An optimizing processing part 22 optimizes delay for the unit of sub-block on the basis of the area for the unit of sub-block stored in the area value information storage part 3, the curve of correspondence between area and number of cells stored in an area versus cell number curve storage part 8, the area information or delay information of respective circuit blocks in the technology library 4 and a delay limit held in a delay limit holding part 5.
|
