| 摘要 |
Described is a process for manufacturing a semiconductor integrated circuit device, to expose semiconductor regions over the surface of a semiconductor substrate in self-alignment to wiring lines (including gate electrodes) and element isolating regions when forming connection holes. The process includes a first step of coating a semiconductor substrate with a first conductive film, a first insulating film and a second insulating film sequentially, and patterning these films to form first conductive film patterns. A third insulating film is then formed over the semiconductor substrate, on the side walls of the first conductive film patterns and over the second insulating film, and a fourth insulating film is formed over the third insulating film. After forming the third and fourth insulating films, a mask for a first opening between adjoining ones of the first conductive film patterns is formed over the fourth insulating film, and the fourth insulating film exposed from the first opening of the mask is etched, under conditions that the fourth insulating film is more easily etched off than the third and second insulating films, to form a second opening in the fourth insulating film. Thereafter, the third insulating film, as exposed through the second opening, is anisotropically etched under conditions that the third insulating film is more easily etched off than the first insulating film and the fourth insulating film, to form a third opening.
|
