发明名称 |
Semiconductor integrated circuit device having a hierarchical power source configuration |
摘要 |
A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in voltage between the sub source voltage transmission line and the main source voltage transmission line to operate at high speed with low current consumption.
|
申请公布号 |
US6236613(B1) |
申请公布日期 |
2001.05.22 |
申请号 |
US20000547283 |
申请日期 |
2000.04.11 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OOISHI TSUKASA |
分类号 |
G11C11/413;G11C5/14;G11C7/06;G11C7/14;G11C8/14;G11C11/401;G11C11/407;G11C11/4074;G11C11/408;G11C11/409;G11C11/4094;H01L21/822;H01L21/8238;H01L21/8242;H01L27/04;H01L27/092;H01L27/108;H03K19/00;(IPC1-7):H03K19/094 |
主分类号 |
G11C11/413 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|