| 摘要 |
A voltage controlled oscillator has first and second complementary output terminals. A first edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the first complementary output terminal. A first comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the first edge delay circuit. The second input terminal is coupled to the first complementary output terminal. The first comparator output terminal is coupled to the second complementary output terminal. A second edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the second complementary output terminal. A second comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the second edge delay circuit. The second input terminal is coupled to the second complementary output terminal. The second comparator output terminal is coupled to the first complementary output terminal. The control inputs of the first and second comparators and the first and second edge delay circuits are coupled together and adapted to allow each circuit to transition from at least one logic level to another logic level at a rate responsive to the magnitude of a signal applied thereto. A feedback circuit is coupled between the first and second complementary output terminals and the third inputs of the first and second comparator circuits.
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