| 摘要 |
A fractional synthesis approach and arrangement are presented which achieve fine frequency resolution with low phase noise while at the same time retaining a high phase comparison frequency/fast frequency changing speed. An output signal having a desired output frequency is generated by a voltage controlled oscillator (VCO). An output divider divides the output frequency by an output divisor N to produce an output pulse train. The output divisor N may be equal to an output integer N or the output integer plus one N+1, for example, and may change during the generation of a single output frequency. For different desired output frequencies, the value of the output integer N may be varied. A reference divider divides a reference frequency by a reference divisor M to produce a reference pulse train. The reference divisor M may be equal to a reference integer M or the reference integer plus one M+1, for example, and may change during the generation of a single output frequency. A fractional controller may vary the value of the divisor M between successive pulses from the reference divider to produce a mean output pulse frequency having a non-integral relationship to the reference frequency. A phase error detector compares the pulse trains and generates a phase error signal. This signal, which may be filtered or other wise processed, controls the VCO to produce the output signal at the desired output frequency.
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