| 摘要 |
A system and method for providing a sustained, peak performance computing architecture is provided. A hardware processing architecture is provided for performing repeated algorithm iterations, wherein each of the algorithm iterations is performed on a parallel set of algorithm input data. The architecture includes a memory arranged to store the algorithm input data in parallel, contiguous bit locations. A parallel execution module having a plurality of functional execution units is provided, each of the functional execution units being configured to perform a preassigned function dictated by the algorithm on predetermined bits of each iterative parallel set of algorithm input data. A data flow module is coupled to the memory and to the parallel execution module, and is configured to replicate in hardware the control constructs and expression evaluations of the algorithm, and to distribute the input data to the plurality of function execution units in accordance with the control constructs and expression evaluations of the algorithm.
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