Floating gate semiconductor device with reduced erase voltage

摘要

The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.