发明名称 |
Avoiding livelock when performing a long stream of transactions |
摘要 |
An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.
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申请公布号 |
US6237055(B1) |
申请公布日期 |
2001.05.22 |
申请号 |
US19980205024 |
申请日期 |
1998.12.03 |
申请人 |
INTEL CORPORATION |
发明人 |
TRIEU TUONG;LENT DAVID D.;BOGIN ZOHAR;GADAGKAR ASHISH |
分类号 |
G06F13/364;(IPC1-7):G06F13/362;G06F13/14 |
主分类号 |
G06F13/364 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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