| 摘要 |
PROBLEM TO BE SOLVED: To provide a dynamic RAM of one intersection point type in which operation margin is improved and chip area per bit is reduced. SOLUTION: The dynamic RAM is provided with plural bit lines, plural word lines, plural memory mats which include plural memory cells coupled to the plural bit lines and the plural word lines and arranged in the direction of the bit line, and with a row of sense amplifiers provided in a region between memory mats arranged in the direction of the bit lines and comprising plural latch circuits in which input/output nodes are connected to half of bit lines provided in these memory mats. For normal memory mats excluding both end parts in the direction of the bit lines, any one word line of memory mats is activated, and for end memory mats provided at both ends in the direction of the bit lines, word lines of both memory mats are simultaneously activated. |
