| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory whose operation speed of reading out data can be increased. SOLUTION: This memory has a memory cell array 20 consisting of plural memory cells 21, word lines 12 having the same number as the number of rows of the memory cells 21 are connected respectively to gates of the memory cells 21. Also, bit lines 13 having the same number as the number of lines of the memory 21 cells are connected respectively to connection points of sources and drains of the memory cells 21. An inverter 24 and a NAND element 23 are connected to each word line in series. The bit lines 13 make a pair, a sense amplifier and a pre-charge circuit 6 are connected to the mutual connection point of one end side of the bit lines 13 through a digit line 60, and a virtual GND and a pre-charge circuit 10 are connected to the other end side through the digit line 60. A bank selecting line 32 is connected to the bit line 13, and bank selecting drivers 3a to which the NAND element 30 and an inverter 31 are connected in series are connected to both ends of each bank selecting lines 32.</p> |
