| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor and a debug device for executing the management and instruction address calculation of a program counter at low cost with high performance. SOLUTION: When an instruction decoder 6 decodes a branch instruction, the destination of branch address is obtained by adding either the contents of a first pre-fetch counter 7 or the contents of a second pre-fetch counter 8, the output of a carry input control circuit 10, and a branch offset value read from an instruction buffer 5 one time. Thus, it is possible to quickly execute branch address calculation without making it necessary to provide any constant generating circuit of which hardware scale is large, or increasing the hardware quantity of an adder.
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