| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a data transmission speed conversion circuit that can normally output data whose transmission speed is converted without causing a slip error. SOLUTION: In the case of converting input data with 64 KHz into data with 2.048 MHz, a synchronizing signal generating section 7 generates an output data synchronizing signal (TSYNC) with timing not causing a slip error in the case that a P/S conversion section 3 conducts P/S conversion on the basis of a frame signal (HWRSYNC) at a 2.048 MHz I/F side and a data transfer clock (64 KHz) at the side of 64 KHz I/F. Furthermore, in the case of converting input data of 2.048 MHz into data of 64 KHz, the synchronizing signal generating section 7 generates an input data synchronizing signal (RSYNC) of timing not causing a slip error in the case that a P/S conversion section 6 conducts P/S conversion on the basis of a frame signal (HWTSYNC) at the 2.048 MHz I/F side and a data transfer clock (64 KHz) at the side of 64 KHz I/F.</p> |
