发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To execute a boundary scan test in one round by means of a small number of pins in a stacked device 41, which is formed integrally by sealing a plurality of chips ic1a, ac2a, ic3a. SOLUTION: A register, such as BSR in addition to a core logic, is mounted on each of chips ic1a to ic3a, a TAPC which controls the register is provided to the chip ic1a alone of a first stage and signal lined TDO, TDI for test order/ data output and input of a boundary scan test are connected in a loop via a wire WOI which connects chips. The chip ic1a distributes other signal lines TCK, TMS. TRST used for a test from its output signal lines TAP0 to TAP4. Thereby, a test can be the cuted in one round, by means of a small number of pins and to cut the man-hours and an area of the chips ic2a, ic3a whereon a TAPC is not mounted.
申请公布号 JP2001135786(A) 申请公布日期 2001.05.18
申请号 JP19990318485 申请日期 1999.11.09
申请人 SHARP CORP 发明人 MIYAJI HISAMI;YAMASHITA TOSHIFUMI
分类号 G01R31/28;G01R31/3185;G11C29/00;H01L21/66;H01L21/822;H01L25/065;H01L25/07;H01L25/18;H01L27/04;(IPC1-7):H01L25/065 主分类号 G01R31/28
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