发明名称 Anordnung mit einer mehrschichtigen Leiterplatte und einem Träger
摘要 A unitized multilayer circuit structure (10) includes a plurality of planar dielectric insulating layers (11) stacked in laminar fashion to form a substrate. The substrate has sides formed by edges of the dielectric insulating layers (11). Recessed regions (15, 13) are formed in one or more sides of the substrate for use in attaching the unitized multilayer circuit structure (10) to a higher level assembly or for attaching electrical contact circuitry (17) to the unitized multilayer circuit structure (10). <MATH>
申请公布号 DE69520624(D1) 申请公布日期 2001.05.17
申请号 DE1995620624 申请日期 1995.08.25
申请人 RAYTHEON CO., LEXINGTON 发明人 YOUNG, BRIAN D.
分类号 H05K1/14;H01L23/13;H01L23/538;H05K1/00;H05K1/03;H05K1/18;H05K3/34;H05K3/46;(IPC1-7):H01L23/13;H01L23/498 主分类号 H05K1/14
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