发明名称 |
DE-INTERLEAVE CIRCUIT |
摘要 |
<p>To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a de-interleave memory (4) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory (4) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory (4) only requires space for one superframe. <IMAGE></p> |
申请公布号 |
EP1100202(A1) |
申请公布日期 |
2001.05.16 |
申请号 |
EP19990929763 |
申请日期 |
1999.07.08 |
申请人 |
KABUSHIKI KAISHA KENWOOD |
发明人 |
SHIRAISHI, KENICHI;SHINJO, SOICHI;HORII, AKIHIRO |
分类号 |
H04N19/423;G06F12/00;H03M1/00;H03M13/27;H04B7/185;H04L25/40;H04L27/06;H04N7/08;H04N7/081;H04N7/24;H04N19/00;H04N19/426;H04N19/44;(IPC1-7):H03M1/00 |
主分类号 |
H04N19/423 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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