Computing apparatus for double-precision multiplication

摘要

In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result. In this case, at least two digits are set before the decimal point, thereby allowing each of the products of the high-order word/low-order word of the double-precision multiplicand and the high-order word/low-order word of the double-precision multiplier, to be obtained at a bit width which is larger by at least one bit than a bit width of double precision.