| 摘要 |
PURPOSE: A dual phase detector is provided to achieve the high speed operation of the dual phase detector by reducing the jitter component and saving the initial locking time of the dual phase detector. CONSTITUTION: The device includes the first type phase detector(71) which selectively generates the first up signal or the first down signal. The second type phase detector(72) generates both the second up signal and the second down signal. A selection control section(75) generates a selecting signal by logically combining an input clock, the first up and down signals and the first and second down signals. A pair of MUX sections(73,74) are provided to select one of the first and second up signals and one of the first and second down signals. The phase of the input clock is matched with the phase of the output clock by the final up and down signals selected by the mux sections(73,74).
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