发明名称 Semiconductor memory
摘要 A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, thereby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.
申请公布号 USRE37176(E1) 申请公布日期 2001.05.15
申请号 US19990256500 申请日期 1999.02.23
申请人 HITACHI, LTD. 发明人 KAJIGAYA KAZUHIKO;SATO KATSUYUKI
分类号 G11C11/401;G11C11/409;G11C11/4096;(IPC1-7):G11C7/00 主分类号 G11C11/401
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