| 摘要 |
PURPOSE: A technique for minimizing gate charge and gate to drain capacitance in power MOS devices such as DMOS, IGBTs and MOSFETs is provided to lessen in interelectrode capacitance. CONSTITUTION: The power MOS device includes a MOS semiconductor substrate layer having one or more source regions and one or more drain regions, a gate insulator covering the semiconductor substrate, characterized in that a conductive gate on gate insulator, a channel underneath the gate and between a source region and a drain region for passing current between the source and the drain when a voltage is applied to the gate, a means for reducing a capacitance between the gate and drain.
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